Astera Labs in San Jose, CA is seeking a Technical Lead Digital Design Engineer to drive RTL implementation of complex SoC blocks. You will work from micro-architecture through silicon bring-up, partnering with verification, PD and DFT teams to deliver high-performance connectivity solutions.
You’ll apply SystemVerilog, Python scripting, and upstream design flows with Synopsys/Cadence toolchains, ensuring timing closure and robust DFT features while mentoring junior engineers in a fast-paced,
#J-18808-LjbffrTechnical Lead, High-Speed Digital IC Design in san jose at Unknown Company
This position is listed as full time and onsite.