Astera Labs is scaling the connectivity fabric behind the world's largest AI clusters, and reliable power delivery is non-negotiable in the SoCs we ship. As a Technical Lead Physical Design Engineer- Power Integrity, you will own IR drop and electromigration analysis and closure across Astera Labs' connectivity ASIC portfolio, driving power integrity from early floorplan through tapeout.
You will partner with power grid, floorplan, package, and implementation teams to ensure stable power
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