Astera Labs is scaling the connectivity fabric behind the world’s largest AI clusters, and reliable power delivery is non-negotiable in the SoCs we ship. As a Technical Lead Physical Design Engineer- Power Integrity, you will own IR drop and EMIR analysis and closure across Astera Labs' connectivity ASIC portfolio, driving power integrity from early floorplan through tapeout.
You will partner closely with power grid, floorplan, package, and implementation teams to ensure stable power delivery,
#J-18808-LjbffrTech Lead: Power Integrity & IR/EM for SoCs in san jose at Unknown Company
This position is listed as full time and onsite.