Astera Labs is seeking a Tech Lead Engineer to drive front-end digital design for high-performance switch ASICs that enable rack-scale AI infrastructure. In CCE2, you will translate microarchitecture into robust RTL and lead block-level execution across synthesis, timing, verification, DFT, and physical implementation.
This is an opportunity to own critical connectivity technology from architecture through GDS while partnering across design, verification, physical design, and systems teams.
#J-18808-LjbffrTech Lead Engineer - Front-End Digital ASIC Design in san jose at Unknown Company
This position is listed as full time and onsite.