Astera Labs in San Jose is seeking a Tech Lead Design Engineer to architect and deliver the connectivity silicon powering AI clusters. You will own RTL design for blocks from microarchitecture through tapeout and work at the cutting edge of PCIe, CXL, Ethernet, and UALink technologies.
This high-impact role partners with architecture, verification, DFT and physical design teams to take features from spec to silicon, while contributing to the design methodology that scales with our roadmap.
#J-18808-LjbffrTech Lead Design Engineer - RTL & Silicon Architect in san jose at Unknown Company
This position is listed as full time and onsite.