SystemVerilog/UVM Verification Engineer — RTL & Automation

Selby Jennings is partnering with a leading technology-driven trading firm that designs high-performance compute platforms used in real-time production environments. The hardware group develops custom FPGA and ASIC solutions, and we are seeking Design Verification Engineers with ownership over verification methodology, automation, tooling, and infrastructure.

You will develop SystemVerilog/UVM testbenches, drive coverage, debug RTL, and collaborate with hardware designers across FPGA, ASIC, SoC,