Static Timing Analysis Design Engineer / Physical Design

We are seeking an experienced engineer for SoC Static Timing Analysis for advanced semiconductor products. This role will own end-to-end Timing Constraints and Static Timing Analysis across complex designs, driving initial constraints  development and timing correlation in early stages to final Timing Signoff for cutting-edge technology nodes. This role would work with implementation engineers from synthesis through final timing closure to close timing, including timing correlation, debugging failing timing paths, providing timing ECOs (automated and manual).The ideal candidate demonstrates technical timing and constraints expertise to close timing on a given design on silicon along with capability of using timing analysis tools to correlate timing and generate automate as well as manual timing fixes.Key Responsibilities1.

End-to-End Constraints and Timing Signoff OwnershipDrive Timing Constraints Creation and ValidationWork with Frontend, IP and DFT teams to Validate Constraints, Resolve timing issuesWork hand-in-hand with Implementation owner(s) and Full Chip STA team to close TimingTiming Correlation and Timing Path Debug from synthesis through timing signoffProvide timing feedback during all design stagesCreate Automated and Manual timing fixes for implementation2. Team Leadership & Organization DevelopmentParticipate career development.Interface with Implementation owner(s) and Full Chip STA team.3. Technical Strategy & InnovationProvide feedback to improve scalability, productivity, and design quality through methodology enhancements to leadership4.

Cross-Functional & Ecosystem EngagementCollaborate with Frontend, IP and DFT teams for Constraint Validation and Timing IssuesSupport post-silicon bring-up, yield improvement, and production ramp activities.Core Technical ExpertiseSTA and signoff methodologiesTiming ECO Generation (automated and manual)Constraints Development and ValidationAdvanced node implementation ( 16nm / 5nm)Scripting in Python, TCL, and PerlFamiliarity with using AI to generate scriptsRequired QualificationsBachelor’s or Master’s in Electrical / Electronics Engineering or related field3-6 years of experience in ASIC / SoC Timing AnalysisStrong knowledge of industry STA tools (Synopsys flows)Strong communication skillsPreferred QualificationsExperience in high-reliability SoCsExposure to AI-driven design methodologies and automationWhy This Role MattersTiming closure of flagship SoCs at advanced nodesDirect impact on silicon success and product competitivenessMore information about NXP in the United States...NXP is an Equal Opportunity/Affirmative Action Employer regardless of age, color, national origin, race, religion, creed, gender, sex, sexual orientation, gender identity and/or expression, marital status, status as a disabled veteran and/or veteran of the Vietnam Era or any other characteristic protected by federal, state or local law. In addition, NXP will provide reasonable accommodations for otherwise qualified disabled individuals.#LI-6692SummaryLocation: Austin (Oakhill, Office)Type: Full time