Renesas is seeking an experienced Staff Design Verification Engineer to join our team focused on memory interface products for data center, AI, and cloud computing applications. You will verify advanced memory data buffer products, including DDR6 and future generations, using SystemVerilog/UVM environments and testbenches.
Ideal candidates bring 8+ years in semiconductor design verification, strong SystemVerilog/UVM expertise, and a track record of owning complex verification assignments from
#J-18808-LjbffrStaff Memory Verification Engineer - SystemVerilog/UVM in duluth at Unknown Company
This position is listed as full time and onsite.