Staff Engineer, Serdes Analog Design

Staff Engineer, Serdes Analog DesignSan Jose, California, United StatesAdvancing the World's Technology TogetherOur technology solutions power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you'll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of what's possible and powering the future.We believe innovation and growth are driven by an inclusive culture and a diverse workforce. We're dedicated to empowering people to be their true selves.

Together, we're building a better tomorrow for our employees, customers, partners, and communities.Samsung Semiconductor Inc. (SSI) is advancing the world's technology. As a leader in Memory, System, LSI and LCD technologies, our US teams contribute to breakthroughs in 5G, SOC, memory and display.

With our global perspective and diversity of thought, we proudly serve our customers around the world. We are looking for team members who share our commitment to learning and growth and excel when collaborating within and across teams.Location: Daily onsite presence at our San Jose, CA headquarters in alignment with our Flexible Work policyWhat You'll DoIn this role, you will actively work on architecture and circuits of high-speed interconnect transceiver (Serdes). You will work on circuits for Serdes IPs, clock generation as well as traditional analog circuits.You'll work with a team to develop high-performance and low-power serdes, including display interface, camera sensor interface, UCIe / die-to-die interconnect and 224/448Gbps UA-link/Ethernet using cutting-edge process technologies.Location: Daily onsite presence at our San Jose, CA headquarters in alignment with our Flexible Work policyDesign low-power and low-voltage analog and custom digital circuit components using advanced CMOS process technologiesTranslate component design specification to schematics.

Build simulation test-benches to evaluate circuit performance, functionality, power consumption and reliability.Supervise layout designers to generate LVS/DRC clean layout. Optimize layout to improve the power consumption and performance of circuitsFunctionality and performance validation in SiliconWhat You BringBachelors with 10+ years, Masters with 8+ years or PhDs with 5+ years of experience.Minimum 2+ yrs experience RF/Analog/Serdes SoC design experience.Knowledge and experience with analog circuits/mixed signal circuits: such as bandgap, LDO, filters.Knowledge and experience with circuits of Serdes IPS: CTLE, DFE, FFE, clock distributions, PI, IQ generation.Knowledge of Serdes architecture and high-speed interconnect standard (USB, PCIe, UCIe)Knowledge and experience with ESD, PLL, clock generation, ADC, DAC is a big plus.Well-versed in EDA tools (Cadence, Spectre, Totem, EMX)Comfortable with scripting languages (Python, Matlab)You're inclusive, adapting your style to the situation and diverse global norms of our people.An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.You're collaborative, building relationships, humbly offering support and openly welcoming approaches.Innovative and creative, you proactively explore new ideas and adapt quickly to change.