Staff Design Verification Engineer (SystemVerilog/UVM)

Analog Devices, Inc. in Chandler, AZ seeks a Staff Engineer in Design Verification to define interfaces, verify state machines, and build metric-driven SystemVerilog/UVM environments for data center, energy, and automotive applications.

You will develop directed and constrained random tests, write Verilog-AMS and Real Number Models, and contribute to product definitions while enjoying a partial telecommute option.