A leading technology company in San Jose is seeking a Staff Design Verification Engineer to oversee the verification lifecycle for complex AI connectivity ASICs. The ideal candidate will have over 5 years of experience, strong proficiency in SystemVerilog/UVM, and skills in debugging and collaborative problem-solving. This position offers a base salary range of $160,000 to $195,000, plus bonuses and a diverse, inclusive working environment.
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Staff Design Verification Engineer - AI Connectivity ASICs in san jose at Unknown Company
This position is listed as full time and onsite.