NVIDIA Corporation in Santa Clara is seeking a skilled SRAM circuit designer to drive embedded SRAM design and compiler development for advanced silicon. You will collaborate with SOC design, silicon test, and productization teams to optimize power, performance, and area across next‑gen GPUs and AI accelerators.
The role requires a BSEE (or equivalent) with 2+ years in SRAM design (MSEE/PhD preferred), familiarity with Cadence Virtuoso, and a proactive approach to applying AI tools in daily
#J-18808-LjbffrSRAM Design Engineer — AI-Driven IP & Compiler Innovation in santa clara at Unknown Company
This position is listed as full time and onsite.