Sr. Staff PCB Design Engineer

At d-Matrix, we are focused on unleashing the potential of generative AI to power the transformation of technology. We are at the forefront of software and hardware innovation, pushing the boundaries of what is possible. Our culture is one of respect and collaboration.We value humility and believe in direct communication. Our team is inclusive, and our differing perspectives allow for better solutions. We are seeking individuals passionate about tackling challenges and are driven by execution.  Ready to come find your playground? Together, we can help shape the endless possibilities of AI. Role OverviewAs Sr. Staff PCB Design Engineer, you will lead the physical design of the boards that connect d-Matrix's AI silicon to the world. Our "Corsair" platforms push the limits of signal density and power delivery, and you will own layout for high-complexity, high-layer-count PCBAs (20+ layers) — ensuring 112G/224G SerDes signals stay clean and thousands of amps are delivered with minimal loss. Beyond hands-on layout, you will serve as custodian of our Design Methodology, driving the automation, tooling, and constraint management processes that let hardware development scale with precision and speed. You'll partner closely with power, ASIC, and manufacturing teams, and have the autonomy to build layout infrastructure from the ground up.What You Will DoLead full-cycle layout for high-complexity AI accelerator cards (PCIe form factors) and system baseboardsArchitect and manage the Constraint Manager (CM) hierarchy in Cadence Allegro, defining the source of truth for high-speed routing rules and electrical constraintsDevelop automation scripts (SKILL, Python, or TCL) to streamline layout tasks, DRC checks, and reportingExecute layout for ultra-high-speed interfaces including PCIe Gen5/6, CXL, and custom die-to-die (D2D) interconnectsPartner with Power Engineers on PDN strategy, including multi-phase VRM layouts and decoupling capacitor placement for high-TDP ASICsDrive PCB stack-up definition, including advanced low-loss materials (e.g., Megtron 7/8) and hybrid build-upsServe as primary interface with fabricators and CMs to ensure DFM, DFT, and DFA requirements are met for high-yield productionWhat You Will BringBS in Electrical/Electronic Engineering or equivalent practical experience10+ years of experience in high-speed, high-density PCB layout for servers, networking, or AI acceleratorsProficiency in Cadence Allegro Constraint Manager, including T-junctions, differential pair phase-tuning, and Z-axis delay matchingProven ability to write and deploy SKILL scripts or use Allegro's API to automate design audits and layout routinesDeep understanding of high-speed routing techniques (back-drilling, via-in-pad, skip-vias) and HDI/ELIC designProven track record routing 112G SerDes and complex DDR5/HBM interfacesPreferred QualificationsExperience establishing a Library Management System and standardized footprint/padstack creation processesFamiliarity with PLM/PDM integration for managing layout releases and ECO workflowsKnowledge of PCB warpage mitigation strategies for large-form-factor ASICs and MCMsEqual Opportunity Employment Policyd-Matrix is proud to be an equal opportunity workplace and affirmative action employer. We’re committed to fostering an inclusive environment where everyone feels welcomed and empowered to do their best work. We hire the best talent for our teams, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status. Our focus is on hiring teammates with humble expertise, kindness, dedication and a willingness to embrace challenges and learn together every day.d-Matrix does not accept resumes or candidate submissions from external agencies. We appreciate the interest and effort of recruitment firms, but we kindly request that individual interested in opportunities with d-Matrix apply directly through our official channels. This approach allows us to streamline our hiring processes and maintain a consistent and fair evaluation of al applicants. Thank you for your understanding and cooperation.

Compensation Range: $175K - $265KLocationSanta ClaraEmployment TypeFull timeLocation TypeHybridDepartmentSystems EngineeringCompensation$175K – $265K • Offers Equity • Offers BonusThe pay range below is for all roles at this level across all US locations and functions. Individual pay rates depend on a number of factors—including the role’s function and location, as well as the individual’s knowledge, skills, experience, education, and training. We also offer incentive opportunities that reward employees based on individual and company performance. This is in addition to our diverse package of benefits centered around the wellbeing of our employees and their loved ones. In addition to the usual Medical/Dental/Vision/401k, our inclusive rewards plan empowers our people to care for their whole selves. An investment in your future is an investment in ours.