Our Machine Learning Acceleration (MLA) team develops the Inferentia and Trainium SoCs that power today’s AI workloads in datacenters worldwide. As a Sr. EMIR Engineer, you’ll contribute to the EMIR sign‑off of our SoCs and help maintain a high bar on quality.
Key job responsibilities
- Design & analyze power grids
- Setup flows for EMIR analysis
- Run EMIR analysis for large subsystems and SoCs
- Partner with EDA tool vendors to develop/evaluate new methodologies for EMIR analysis
- Develop and maintain dashboards for EMIR rollups
- Work with designers, architects, verification engineers and physical design engineers to develop vectors for IR analysis, thermal analysis, and power estimation
A day in the life
- Design and evaluate power grids
- Work with designers, architects and verification engineers to develop worst‑case vectors for power and IR analysis
- Root‑cause low annotation or low switching coverage with vectors
- Develop & maintain dashboards to track EMIR status
- Root‑cause IR drop and suggest solutions to fix
- Combine IR analysis of SoC with IR at board and package level (concurrent IR analysis)
- Do post‑silicon power measurements and correlate with simulation
- Innovate on ways to model VR, board and package impact on voltage drop more accurately
- Partner with EDA tool vendors to develop/evaluate new methodologies for EMIR analysis
About the team
We are a start‑up‑like team where collaboration and flexibility are core. You’ll work with thought leaders in multiple technology areas and with architects, RTL designers, verification engineers, physical design engineers, emulation engineers, and software engineers.
Basic Qualifications
- 5+ years of ASIC implementation, synthesis, STA and physical design in deep sub‑micron nodes (16 nm or smaller)
- BS + 6 yrs or MS + 5 yrs or PhD + 3 yrs in EE/CS
- Expertise on EMIR analysis tools such as Redhawk‑SC, Voltus or similar
- Deep, circuit‑level understanding of power, EM and IR
- Ability to give feedback to RTL designers and physical designers on how to reduce IR
- Highly proficient with scripting languages (Tcl, Perl, Python or similar)
- Good understanding of physical design, EM/IR, power integrity and thermal at die, package, board and server levels
Preferred Qualifications
- Familiarity with Make or similar for automation of EMIR rollups
- Experience with RTL design (SystemVerilog)
- Experience with PnR tools (FusionCompiler or Innovus)
- Familiarity with power analysis tools (PrimePower or similar)
- Familiarity with timing analysis tools (PrimeTime or similar)
- Some experience with lab equipment and capability to do lab power analysis
Amazon is an equal‑opportunity employer and does not discriminate on the basis of protected veteran status, disability, or other legally protected status.
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