SoC Top-Design Engineer (3nm-5nm RTL-to-GDSII)

An innovative technology company in California is seeking an experienced Chip-Level / SoC-Level Design Engineer to join their team. The successful candidate will work on RTL-to-GDSII designs and contribute to SoC-top projects, utilizing tools like Fusion Compiler and ICC2. Key responsibilities include block-level design, scripting in TCL and Python, and working with multi-power domain designs. Familiarity with lower-node technologies is a strong advantage. This role presents an exciting opportunity to innovate within state-of-the-art engineering environments.
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