Apple Inc. in Cupertino is seeking an ASIC power modeling engineer to design and validate power delivery and DVFM points for IPs and SOCs. You will model and optimize power behavior across multiple Apple silicon blocks to support energy-efficient products.
You will collaborate with architecture, design, thermals, PMIC and lab teams to correlate models with hardware data, enabling accurate power predictions and robust silicon performance.
#J-18808-LjbffrSoC Power Modeling Engineer – Optimize AI/ML & IPs in cupertino at Unknown Company
This position is listed as full time and onsite.