SoC Physical Design & Timing Engineer

Apple Inc. in Beaverton, Oregon is seeking a skilled physical design engineer to drive partition-level implementation for a complex SOC. You will collaborate with the logic team from early architecture through netlist to GDS2, ensuring timely delivery and signoff.

The role requires sub-10nm experience, large SOC work, and robust proficiency with standard EDA tools to meet aggressive die-size and performance goals.