SoC Interconnect & RTL Design Engineer

Apple seeks a design engineer to drive RTL development, fabric integration and memory subsystem optimization for SoC blocks. You will own RTL generation, templating and scripting while coordinating with front-end, power and verification teams to ensure timing and quality.

The role requires collaboration with multi-disciplinary groups to deliver high-quality designs on schedule, with a strong emphasis on coherent/non-coherent interconnects and memory hierarchy.