A technology consulting firm is seeking a Design Verification Engineer to join the team for a full-time project. The role involves understanding SV and UVM, building verification environments, and collaborating with various technical teams. Candidates should have solid debugging skills and the ability to develop test plans. Compensation ranges from $80,000 to $160,000, depending on experience and skills.
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SoC Design Verification Engineer | UVM & Power Debug in austin at Unknown Company
This position is listed as full time and onsite.