Velaura in Austin, Texas, seeks Design Verification Engineers to verify its next‑generation Physical AI SoC. You will work with architects, RTL, software and system teams to ensure correctness, performance and safety across the platform.
Responsibilities include developing verification strategies, building environments with SystemVerilog, UVM and C/C++, and driving bug investigation and root-cause analysis across HW/SW boundaries, including emulation and pre‑silicon software bring‑up.
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