Silicon Verification Engineer - RTL, SystemVerilog/UVM

Google Mountain View is seeking a Mid-level Silicon Design Verification Engineer to drive verification of complex digital blocks for next‑generation devices. You will plan, implement, and debug testbenches using SystemVerilog, UVM, and formal methods, collaborating with design verification leads and hardware engineers.

You will verify RTL at the SystemVerilog level, integrate IP cores and memory subsystems, and develop constrained‑random environments, coverage metrics, and debugging strategies