Silicon Design Verification Engineer - UVM & SystemVerilog

AMD is seeking a Silicon Design Verification Engineer in San Jose, CA. You will work in the SOC Verification Team, designing testbenches in SystemVerilog and UVM, and creating robust verification environments for complex IP designs.

You will own block-level test benches, collaborate with RTL to optimize clock gating, and verify performance and power aspects using modern methodologies and tools. A Master’s degree is required, with expertise in SV, UVM, C++, and Python.