Senior VHDL RTL FPGA Engineer for Networking & Timing

Schweitzer Engineering Laboratories, Inc. is hiring a Senior Engineer focused on VHDL RTL digital logic design for FPGA-based products. You will lead RTL projects, create design docs, and develop verification test plans while coordinating with product managers and cross-functional teams.

You will mentor others and contribute to labor estimates, with a focus on Ethernet/Security gateways and timing technologies such as PTP. This is a senior, on-site role in Pullman, WA.