Senior Verification Engineer, Networking ASICs

Advanced Micro Devices, Inc. in Santa Clara, CA, is seeking a Design Verification Engineer to drive verification closure on complex ASIC designs. The ideal candidate will have robust knowledge of SystemVerilog and UVM, and experience in debugging intricate architecture issues.

This role involves developing UVM-based testbench architectures, collaborating with various teams, and optimizing verification plans. The company fosters a culture of innovation, making it a great place for career advancement.