Broadcom's ASIC Products Division is seeking a senior Design Verification Engineer to lead verification planning, test bench development, and coverage closure for complex digital and mixed-signal IP blocks used in ASICs.
The role emphasizes SystemVerilog, UVM, SVA, and advanced verification methodologies, with opportunities to work with emulation platforms and FPGA prototyping. A BS or MS in Electrical/Computer Engineering with 12+ or 10+ years of related experience is required.
#J-18808-LjbffrSenior Verification Engineer - Digital & Mixed-Signal IP in irvine at Unknown Company
This position is listed as full time and onsite.