Senior Timing Methodology Lead for FPGA/ASIC

Altera, located in San Jose, CA, seeks a senior Design Automation engineer focused on Static Timing Analysis and timing modeling for ASIC/IP/FPGA timing flows. You will lead a small team, own production‑grade flows, and drive cross‑functional engagements with design teams and external vendors.

The role emphasizes greenfield characterization, mentoring engineers, and delivering timing sign-off in a unified flow, with AI/ML-infused automation and strong Python/Tcl scripting background required.