Senior Timing Lead Engineer – Ultra-Low-Power SoC

Efficient Computer in San Jose is looking for a Lead STA Engineer to drive timing convergence for their innovative energy-efficient processor. In this cross-functional role, you'll work on cutting-edge fin-FET technologies while collaborating with a team of world-class engineers.

Ideal candidates will have a Master's or PhD in Electrical Engineering, alongside substantial experience in static timing analysis and low-power design. Efficient offers a competitive salary between $200,000 to $250,000 and comprehensive benefits.