Senior SystemVerilog DV Engineer – Equity Eligible

Broadcom Inc. in San Jose, California, is looking for qualified individuals to join their ASIC Product Division. The role involves developing verification environments, analyzing designs, and debugging in a high-performance team. Ideal candidates will have substantial experience in verification methodologies, particularly using SystemVerilog and UVM.

With an annual salary range of $143,800 - $230,000, Broadcom also offers comprehensive benefits including health plans and a 401(k) with matching contributions. Applications are welcome from individuals regardless of background.