Senior Staff Engineer, Digital Verification - ACAS

Senior Staff Engineer, Digital Verification - ACASLocation: San Jose, CA – OnsiteDuration: 6+monthsPay Rate: $90/hr – $100/hrVertical: EngineeringWhat You'll DoCollaborate with RTL Designers and System Architects to define verification specifications.Design test suites for full-chip and block-level verification; develop directed and constrained-random test cases; analyze and debug simulations at RTL and gate levels.Build functional coverage models, collect, and analyze coverage data.Build testbenches for low-power designs; analyze simulations with Hybrid UPF and PG netlists.Manage regression analysis; file and track bugs using bug-tracking systems.RequirementsBachelor's degree with 15+ years of relevant industry experience, Master's with 13+ years, or PhD with 10+ years in Electrical Engineering or related field (preferred).Experience developing testbenches using SystemVerilog UVM, including test case development for constrained-random and directed scenarios.Experience in MCU/CPU verification at both processor and sub-system levels.Strong understanding of CPU architectures and instruction sets (x86, ARM, RISC-V variants), including:Core architecture/micro-architecture verification.Multi-processor cache (L2/L3) coherency and memory hierarchy verification.Good object-oriented programming skills in C++/SystemVerilog; scripting in Python/Perl.Familiarity with Formal Verification.DMS Verification experience or knowledge preferred.Excellent simulation debugging and problem-solving skills.Ability to adopt new methodologies/techniques and promote them across the organization.Experience with EDA tools: Simulators (Synopsys VCS, Cadence Xcelium, Siemens QuestaSim, or equivalent); debugging tools (Synopsys Verdi, Cadence SimVision).For more information, visit LeadStack CareersContact