MediaTek invites applications for a Senior STA Engineer to lead block‑level sign‑off for high‑performance CPU blocks. You will work with PD, RTL, and DFT teams to ensure clean sign‑off and robust timing closures while developing advanced margining techniques.
This role emphasizes collaboration across design disciplines and ongoing contribution to next‑gen margin methodologies. The position requires 5+ years in STA for high‑GHz CPUs, strong knowledge of OCV/AOCV/POCV, and proficiency with
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