Senior STA Design Manager – SoC Timing & Flow

NXP Semiconductors seeks a Static Timing Design Manager for its AI and Chip Engineering SoC Implementation team in Austin. You will lead timing activities for MPU SoCs, develop and verify STA constraints, and drive timing closure across subsystems and full SoCs.

You will collaborate with RTL/IP teams, architecture and DV/EDA vendors to improve timing flows and implement cutting-edge STA methodologies in fast-paced, advanced node projects.