Senior SRAM Layout Engineer — Advanced Memory IP (3nm+)

Tekgence Inc. in Santa Clara, CA seeks a Senior SRAM Layout Design Engineer for a 12‑month contract, onsite at least initially.

You will own the complete custom layout process for SRAM bitcells, memory periphery, test structures, and macros, collaborating with circuit, PnR, CAD, and foundry teams to ensure high-quality memory IP on cutting-edge nodes. You will mentor junior engineers, review layouts, and drive layout quality through verification and best practices.