Senior Space Design Verification Engineer

Viasat is seeking a Senior Design Verification Engineer in the United States to lead RTL verification for FPGA and ASIC designs. You will create tests, develop SystemVerilog/UVM testbenches, and drive coverage and regressions with the RTL team.

You will evaluate tools like Questa, Xcelium and VCS, manage resources, and ensure timely delivery in a fast-paced, site-based environment. Travel up to 10% may be required.