Develop software and tools to automate SoC design and build flows to increase ASIC engineering efficiency. Partner with design and verification engineers and EDA vendors to implement high-speed design methodologies.
Requirements: Requires a degree in Electrical Engineering, Computer Engineering, or Computer Science with 3+ years of EDA tool development experience. Proficiency in hardware description languages like Verilog and programming languages such as C++ or Python is essential.
Key Skills: EDA Tool Development, ASIC Design, SoC Design, Verilog, SystemVerilog, C++, Python, Perl, Tcl, Computer Algorithms, Data Structures, SoC Integration, Synopsys Fusion Compiler, Agentic AI Coding Tools
Benefits: Competitive salaries, Comprehensive benefits package, Equity
#J-18808-LjbffrSenior Software Engineer, SOC Design Methodology in santa clara at Unknown Company
This position is listed as full time and onsite.