Senior SoC Verification Engineer — System-Level Tape-Out

Velaura is seeking a senior Design Verification Engineer to verify a next-generation Physical AI SoC. You will lead system-level verification across boot, root of trust, clock/reset topology, low power, and IO/memory subsystems, coordinating with architects, RTL and firmware teams.

Responsibilities include building SoC verification environments for ARM/RISC-V based CPUs, verifying boot flows and security transitions, and ensuring tape-out readiness.