Astera Labs is seeking a Principal Design Verification Engineer in San Jose, CA to advance verification methodologies for cutting-edge SoCs used in server and networking applications.
The ideal candidate has 8+ years in SoC verification, strong SystemVerilog/UVM expertise, and experience with emulation platforms, test planning, and coverage closure. A Bachelor’s in Electrical Engineering is required; a Master’s is preferred. Competitive salary and benefits offered.
#J-18808-LjbffrSenior SoC Verification Architect (SystemVerilog/UVM) in san jose at Unknown Company
This position is listed as full time and onsite.