Senior SoC Timing Signoff Engineer

Aleron in San Diego, CA, is seeking a Senior SoC STA Engineer to lead chip-level timing sign-off for next-generation SoC designs. This senior technical role focuses on static timing analysis and timing closure while collaborating with multiple teams to ensure timing integrity.

The ideal candidate will possess at least 6 years of hands-on experience, expertise in STA tools like Cadence Tempus, and a strong educational background in electrical engineering. Join a team that values innovation and professional growth!