Senior SoC Physical Design Engineer: Power & Timing

Qualcomm Technologies, Inc. is seeking a candidate to independently plan and perform moderately-defined Physical Design responsibilities for high-speed DDR, graphics, and SOC flows.

The role focuses on optimizing power, performance, and methodology while supporting PDN and timing closure. Responsibilities include floor planning, clock tree synthesis, place-and-route, LVS/DRC checks, and cross-functional collaboration to drive tapeout readiness and signoff.