Senior SoC Physical Design Architect

Celero Communication Inc. in California seeks an experienced Physical Design Engineer to lead the physical implementation of high‑performance SoCs. You will own floorplanning, power grid design, place-and-route, clock tree synthesis, timing closure, and physical verification to deliver manufacturable silicon.

You will collaborate with architecture, RTL, circuit, and verification teams to meet aggressive PPA targets and help tape out next‑generation semiconductor products.