A semiconductor solutions firm is seeking an experienced Senior SoC/ASIC Physical Design Engineer in San Jose or Irvine, CA. The role involves leading chip implementation, refining physical design flows, and collaborating with cross-functional teams. The ideal candidate will have over 10 years of experience in ASIC/SoC design, knowledge of Synopsys tools, and strong PPA optimization skills. This full-time position offers various benefits including equity, medical insurance, and relocation assistance.
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