Intel Foundry's Design Technology Platform (DTP) organization seeks an engineer to lead full-chip floorplanning, custom layout methodologies, and tapeout for advanced-node silicon development vehicles.
You will collaborate across design, process technology, manufacturing, yield engineering and EDA to implement scalable, manufacturable design solutions and automation, with a hybrid work model and opportunities across Hillsboro and other US sites.
#J-18808-LjbffrSenior SoC Layout & Full-Chip Integration Engineer (Hybrid) in phoenix at Unknown Company
This position is listed as full time and hybrid.