Senior SoC Design Engineer: IP Integration & Automation

Cadence Design Systems is seeking an experienced digital design engineer to design and integrate IPs for complex SoCs. You will use Verilog/SystemVerilog, run Lint/CDC checks, and create synthesis constraints for PPA optimization.

You will support verification and physical teams, automate repetitive tasks, and collaborate across multiple disciplines to deliver high-quality designs. Applicants should have 8–12 years of hands-on digital design experience, AMBA/ARM IP familiarity, and strong