Google DeepMind in Mountain View seeks a Silicon Engineer, Power Analysis to design and optimize power for production chips. You will architect power solutions, drive RTL power analysis, and integrate power flows across SoC teams to meet performance and efficiency goals.
Required: 7+ years in ASIC power analysis, tape-outs, Verilog, and industry EDA tools (PowerArtist, PrimeTime, Innovus, etc.), plus scripting in Perl or Tcl. Master’s or PhD preferred; strong collaboration skills a must.
#J-18808-LjbffrSenior Silicon Power Engineer — Automation & Tapeouts in mountain view at Unknown Company
This position is listed as full time and onsite.