Jobtailor in Fremont, CA is seeking an experienced Signal Integrity and Power Integrity engineer to lead high-speed channel design, PDN targeting, and realistic routing rules for PCIe Gen5/Gen6, CXL, NVLink, and DDR5/DDR6 memory.
You will model and simulate with HFSS, ADS, HSPICE, Sigrity; build IBIS-AMI simulations and perform lab validation using oscilloscopes and VNAs to drive corrective design changes across boards, layout, and mechanical teams.
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