HYPERLUME in San Jose, CA is seeking a Principal Design Engineer to lead RTL architecture, design, implementation and verification of advanced SerDes PHY DSP blocks for next‑generation networking and AI products.
In this role you will collaborate with cross‑functional teams to define specifications and deliver high‑performance silicon, with a focus on reliability, scalability and power efficiency.
#J-18808-LjbffrSenior SerDes DSP Design Engineer for AI Networking in san jose at Unknown Company
This position is listed as full time and onsite.