Viasat is seeking a Design Verification Engineer to develop next-generation advanced communications products. Located in Carlsbad, CA, you will collaborate with engineers to verify RTL for secure communications systems.
The ideal candidate has a Bachelor’s in Electrical Engineering, 5+ years in hardware verification using SystemVerilog/UVM, and strong problem-solving skills. This position requires US citizenship and an active security clearance.
Competitive salary from $132,500 to $209,500 annually based on experience.
#J-18808-LjbffrSenior RTL Verification Engineer — FPGA & SystemVerilog Expert in marlborough at Unknown Company
This position is listed as full time and onsite.