Renesas Electronics seeks a senior engineer to design RTL in Verilog for memory data buffer chips used in DDR5/DDR6, supporting data centers and AI workloads. You will work on digital sections of high-performance devices and contribute across architecture, verification, and backend implementation.
The role requires 12+ years in ASIC/IC design, deep RTL expertise, and hands-on experience with synthesis, STA, DFT, and formal methods.
#J-18808-LjbffrSenior RTL Digital Design Engineer – Memory Interfaces in duluth at Unknown Company
This position is listed as full time and onsite.