Senior RTL Design Engineer - Space-Grade ASICs

SpaceX Irvine is seeking a Senior RTL Design Engineer to develop next‑generation ASICs for Starlink satellites and ground infrastructure. You will work with cross‑functional teams across systems, firmware, and ASIC implementation to deliver verified RTL in Verilog/SystemVerilog and ensure timing closure.

You will define micro-architecture, collaborate with verification, and participate in silicon bring‑up while solving clock-domain and power optimization challenges.