HYPERLUME in San Jose, CA is seeking a Senior PHY RTL Design Engineer to own RTL micro-architecture and drive SerDes DSP function development, verification, and timing/power integration. This role requires deep expertise in high-speed digital design and a track record delivering robust PHY IP.
Join a cutting-edge earthtech partner and collaborate with cross-functional teams to ensure reliable silicon that meets performance targets in a rapidly evolving market.
#J-18808-LjbffrSenior RTL Design Engineer — SerDes DSP & Verification in san jose at Unknown Company
This position is listed as full time and onsite.