Senior RTL Design Engineer for LLM Inference ASIC

Acceler8 Talent is seeking an RTL Design Engineer in Palo Alto to help build a next-generation AI accelerator. You will own RTL across ASIC/SoC blocks, driving from architectural concepts through implementation, verification, and tapeout readiness.

The role demands hands-on design leadership, strong Verilog/SystemVerilog expertise, and close collaboration with verification and physical design teams to meet timing, power and area targets.